The present embodiments related to the field of processor design. More specifically, the present embodiments relate conditional branch instructions and processing of the conditional branch instructions.
A processor in a computer system may process an instruction by executing the instruction in a series of steps, or operations. In some cases, to increase the number of instructions being processed by the processor, and therefore increase the speed of the processor, the processor may be pipelined. Pipelining refers to providing separate stages in a processor, wherein each stage performs one or more steps necessary to execute an instruction. As an example of execution instructions in a pipeline, when a first instruction is received, a first pipeline stage may process a small part of the instruction. When the first pipeline stage has finished processing the small part of the instruction, a second pipeline stage may begin processing another small part of the first instruction while the first pipeline stage receives and begins processing a small part of a second instruction. Accordingly, the processor may process two or more instructions at the same time in parallel.
A computer program may include branch instructions, which cause the computer program to branch from one instruction to a target instruction, thereby skipping sequential instructions, if any, if a condition defined by the branch instruction is satisfied. If the condition is not satisfied, the next instruction sequentially after the branch instruction may be executed without branching to the target instruction. Typically, the outcome of the condition being tested is not known until the branch instruction is executed and its condition is tested. Accordingly, the correct next instruction to be executed after the branch instruction may not be known until the condition is tested.
Where a pipeline is utilized to execute instructions, the outcome of the branch instruction may be unknown until branch resolution. The correct next instruction to be executed after the branch instruction may not be known until the branch instruction has passed through one or more stages necessary to determine the outcome of the condition. In some cases, execution of instructions in the pipeline may be stalled, e.g. the stages of the pipeline preceding the branch instruction may not be used to execute instructions, until branch resolution. When the pipeline is stalled, the pipeline is not being used to execute as many instructions in parallel, decreasing overall processor efficiency.
Branch prediction predicts which way a branch will evaluate before fetching, loading, and executing further instructions based on the prediction. To improve processor efficiency, branch prediction may be used to predict the outcome of branch instructions. For example, when a branch instruction is encountered, the processor may predict which instruction, or path, will be executed after the outcome of the condition is known. Then, instead of stalling a pipeline when the branch instruction is issued, the processor may continue issuing instructions beginning with the predicted next instruction. If the branch prediction is correct, then the pipeline would already be loaded with the instructions following the branch, allowing for a faster information flow through the pipeline. However, if the branch prediction is incorrect, then all of the information that was loaded based on the branch prediction must be flushed, causing a significant drop in performance.